The amazing journey from sandcastle to Core i7 processor
STARTING WITH SAND
The deserts of Arizona are home to Intel’s Fab 32, a $3billion factory that’s performing one of the most complicated electrical engineering feats of our time.
It’s here that processors with components measuring just 45 millionths of a millimetre across are manufactured, ready to be shipped out to motherboard manufacturers all over the world.
Creating these complicated miniature systems is impressive enough, but it’s not the processors’ diminutive size that’s the most startling or impressive part of the process.
It may seem an impossible transformation, but these fiendishly complex components are made from nothing more glamorous than sand. Such a transformative feat isn’t simple. The production process requires more than 300 individual steps.
We’ve taken an in-depth look at Intel’s manufacturing method and distilled the whole process into 10 stages. So, to find out how sandcastles become Core i7 processors, read on – and prepare to be amazed.
Step one: Converting sand to silicon
Sand is composed of silica (also known as silicon dioxide), and is the starting point for making a processor. Sand used in the building industry is often yellow, orange or red due to impurities, but the type chosen in the manufacture of silicon is a purer form known as silica sand, which is usually recovered by quarrying.
To extract the element silicon from the silica, it must be reduced (in other words, have the oxygen removed from it). This is accomplished by heating a mixture of silica and carbon in an electric arc furnace to a temperature in excess of 2,000°C.
The carbon reacts with the oxygen in the molten silica to produce carbon dioxide (a by-product) and silicon, which settles in the bottom of the furnace. The remaining silicon is then treated with oxygen to reduce any calcium and aluminium impurities. The end result of this process is a substance referred to as metallurgical-grade silicon, which is up to 99 per cent pure.
This is not nearly pure enough for semiconductor manufacture, however, so the next job is to refine the metallurgical-grade silicon further. The silicon is ground to a fine powder and reacted with gaseous hydrogen chloride in a fluidised bed reactor at 300°C to give a liquid compound of silicon called trichlorosilane.
Impurities such as iron, aluminium, boron and phosphorous also react to give their chlorides, which are then removed by fractional distillation. The purified trichlorosilane is vaporised and reacted with hydrogen gas at 1,100°C so that the elemental silicon is retrieved.
During the reaction, silicon is deposited on the surface of an electrically heated ultra-pure silicon rod to produce a silicon ingot. The end result is referred to as electronic-grade silicon, and has a purity of 99.999999 per cent.
Step two: Creating a cylindrical crystal
Although pure to a very high degree, raw electronic-grade silicon has a polycrystalline structure. In other words, it’s made up of lots of small silicon crystals, with defects called grain boundaries between them. Because these anomalies affect local electronic behaviour, polycrystalline silicon is unsuitable for semiconductor manufacturing.
To turn it into a usable material, the silicon must be turned into single crystals that have a regular atomic structure. This transformation is achieved through the Czochralski Process. Electronic-grade silicon is melted in a rotating quartz crucible and held at just above its melting point of 1,414°C.
A tiny crystal of silicon is then dipped into the molten silicon and slowly withdrawn while being continuously rotated in the opposite direction to the rotation of the crucible. The crystal acts as a seed, causing silicon from the crucible to crystallise around it. This builds up a rod – called a boule – that comprises a single silicon crystal.
The diameter of the boule depends on the temperature in the crucible, the rate at which the crystal is ‘pulled’ (which is measured in millimetres per hour) and the speed of rotation. A typical boule measures 300mm in diameter.
Step three: Slicing the crystal into wafers
Integrated circuits are approximately linear, which is to say that they’re formed on the surface of the silicon. To maximise the surface area of silicon available for making chips, the boule is sliced up into discs called wafers.
The wafers are just thick enough to allow them to be handled safely during semiconductor fabrication. 300mm wafers are typically 0.775mm thick. Sawing is carried out using a wire saw that cuts multiple slices simultaneously, in the same way that some kitchen gadgets cut an egg into several slices in a single operation.
Silicon saws differ from these kitchen tools in that the wire is constantly moving and also carries with it a slurry of silicon carbide, the same abrasive material that forms the surface of ‘wet-dry’ sandpaper. The sharp edges of each wafer are then smoothed down to prevent the wafers from chipping during later processes.
Next, in a procedure called ‘lapping’, the surfaces are polished using an abrasive slurry until the wafers are flat to within an astonishing 2μm (two thousandths of a millimetre). The wafer is then etched in a mixture of nitric, hydrofluoric and acetic acids.
The nitric acid oxides the surfaces to give a thin layer of silicon dioxide – which the hydrofluoric acid immediately dissolves away to leave a clean silicon surface – and the acetic acid controls the reaction rate. The result of all this refining and treating is an even smoother and cleaner surface.
Step four: Making a patterned oxide layer
In many of the subsequent steps, the electrical properties of the wafer will be modified through exposure to ion beams, hot gasses and chemicals. But this needs to be done selectively to specific areas of the wafer in order to build up the circuit.
STAGE FOUR: A multistage process is used to create an oxide layer in the shape of the required circuit features
In some cases, this procedure can be achieved using ‘photoresist’, a photosensitive chemical not dissimilar to that used in making photographic film (just as described in steps B, C and D, below).
Where hot gasses are involved, however, the photoresist would be destroyed, making another, more complicated, method of masking the wafer necessary. To overcome the problem, a patterned oxide layer is applied to the wafer so that the hot gasses only reach the silicon in those areas where the oxide layer is missing. Applying the oxide layer mask to the wafer is a multistage process, as illustrated to the left.
(A) The wafer is heated to a high temperature in a furnace. The surface layer of silicon reacts with the oxygen present to create a layer of silicon dioxide.
(B) A layer of photoresist is applied. The wafer is spun in a vacuum so that the photoresist spreads out evenly over the surface before being baked dry.
(C) The wafer is exposed to ultraviolet light through a photographic mask or film. This mask defines the required pattern of circuit features. This process has to be carried out many times, once for each chip or rectangular cluster of chips on the wafer. The film is moved between each exposure using a machine called a ‘stepper’.
(D) The next stage is to develop the latent circuit image. This process is carried out using an alkaline solution. During this process, those parts of the photoresist that were exposed to the ultraviolet soften in the solution and are washed away.
(E) The photoresist isn’t sufficiently durable to withstand the hot gasses used in some steps, but it is able to withstand hydrofluoric acid, which is now used to dissolve those parts of the silicon oxide layer where the photoresist has been washed away.
(F) Finally, a solvent is used to remove the remaining photoresist, leaving a patterned oxide layer in the shape of the required circuit features.
Step five: Creating n-type and p-type regions
The fundamental building block of a processor is a type of transistor called a MOSFET – you can see how they work below. The type of device illustrated there is a ‘p-channel’ MOSFET (so-called because it uses p-type material). Processors also use ‘n-channel’ MOSFETs, which use n-type material.
MOSFET DESIGN: MOSFETs are the switches at the heart of processor design
The first step in creating a circuit is to create n-type and p-type regions. Below is the method Intel uses for its 90nm process and beyond:
(A) The wafer is exposed to a beam of boron ions. These implant themselves into the silicon through the gaps in a layer of photoresist to create areas called ‘p-wells’. These are, confusingly enough, used in the n-channel MOSFETs.
A boron ion is a boron atom that has had an electron removed, thereby giving it a positive charge. This charge allows the ions to be accelerated electrostatically in much the same way that electrons are accelerated towards the front of a CRT television, giving them enough energy to become implanted into the silicon.
(B) A different photoresist pattern is now applied, and a beam of phosphorous ions is used in the same way to create ‘n-wells’ for the p-channel MOSFETs.
(C) In the final ion implantation stage, following the application of yet another photoresist, another beam of phosphorous ions is used to create the n-type regions in the p-wells that will act as the source and drain of the n-channel MOSFETs.
This has to be carried out separately from the creation of the n-wells because it needs a greater concentration of phosphorous ions to create n-type regions in p-type silicon than it takes to create n-type regions in pure, un-doped silicon.
(D) Next, following the deposition of a patterned oxide layer (because, once again, the photoresist would be destroyed by the hot gas used here), a layer of silicon-germanium doped with boron (which is a p-type material) is applied.
MOSFET CREATION: The properties of the silicon are modified to produce n-type and p-type regions
Step six: Adding gates to complete the MOSFETs
With the n-type and p-type regions in place, all that is needed to complete the MOSFETs is the gate. As with many of these steps, the first job is to produce a patterned oxide layer as described in Step 4. In this case, the oxide layer will have gaps only in the gate regions of the MOSFETs. Again, there are different ways of making the gates, but the method described here is typical.
As shown in the diagram in the ‘Understanding MOSFETs’ box, the first part of the gate is a very thin insulating layer of silicon dioxide, deposited on the surface of the silicon between the source and the drain. This is done using chemical vapour deposition (CVD), a process that takes place in a furnace filled with various gases that cause a chemical reaction to take place on the surface of the silicon.
To complete the MOSFET, a layer of silicon is applied over the top of the thin oxide layer to act as a conductor. Again, CVD is used, and the silicon is applied via an oxidation reaction in which gaseous silicon hydride reacts with oxygen to give silicon and water as products.
Step seven: Connecting the MOSFETs with copper tracks
Once all of this has been done, the wafer will contain billions of MOSFETs. In order for them to work together as circuits, they need to be connected together to produce lots of individual chips, each of them still containing millions of MOSFETs. The process used by Intel is as follows:
(A) The initial state of the MOSFETs on the wafer.
(B) Before the addition of copper circuitry can be carried out, a layer of insulation has to be applied to the wafer so that the interconnecting tracks don’t short all the MOSFETs. Silicon dioxide is used as the insulator, and this layer is built up on the surface of the wafer either by oxidising it in a furnace or by a process of chemical vapour deposition.
With the entire surface of the wafer covered in an insulating layer of silicon dioxide, it’s no longer possible to make connections to the source, drain and gate of the MOSFETs.
There are a number of ways of restoring connections, but for simplicity’s sake we’re going to describe an up-and-coming method called ‘double damascene’. This method involves two damascene steps – one to create tungsten connecting pins and the second to make copper interconnects.
(C) Hydroflouric acid is used to etch holes in the silicon dioxide insulation (through a layer of photoresist).
(D) After that, trenches in the pattern of the required interconnection tracks are etched into the silicon dioxide through another photoresist layer.
(E) A top layer of copper is then applied by electroplating. This fills the trenches and holes to make contact with the underlying MOSFETs. The resultant metallic pins that protrude through the insulating layer are called ‘vias’.
(F) The wafer is now covered in a layer of copper. The final stage is to take this off. In a process called chemical-mechanical polishing, the excess copper is removed so that the desired amount is left to form tracks in the trenches and holes.
FINAL STAGES: An insulating layer of silicon dioxide protects the MOSFETs. Holes etched through it permit connections to be made
Step eight: Completing the circuit
It’s not always feasible to wire up a circuit without wires crossing. If there was just one rogue interconnection, any tracks that crossed would short. To avoid this, MOSFETs have more than one metallic layer, each insulated by another layer of silicon dioxide and connected using vias.
Step nine: Sorting the good chips from the bad
All being well, the wafer should now contain a couple of hundred dies (the official name for chips), but in reality, not all of them will work correctly. Semiconductor manufacturers tend not to publish these figures, but industry experts consider a typical yield (the percentage of working dies on a wafer) to be about 60 per cent.
The next job is therefore to find out which dies are working, a task that is carried out by a wafer probe. This piece of hardware uses pins that line up with the contacts on a die, through which electrical signals can be passed to put the processor through its paces.
To sort the wheat from the chaff, dies are categorised as ‘functional’ or ‘non-functional’, but there might also be several examples of partially functional dies. Processors in which only some of the dies are working can still be sold as a lower-specification product. After all of the dies have been tested, the wafer is sawn up into individual dies that are sorted and deployed according to the results of the wafer test.
Step ten: Packaging to survive the real world
We might have a fully working die now, but, as it stands, it’s much too fragile to ship to a motherboard manufacturer. Furthermore, the die has hundreds or thousands of connections to the outside world, but it’s only a few millimetres square, making it far too fiddly for an electronics company to make connectors for it.
The final step, therefore, is to encase the bare chip into a package that most people would think of as a ‘processor’. Several methods are available for this process. Whichever one is used, the end result is that the die is firmly attached to the package, and electrical connections are made between the contacts on the die and the contacts on the package.
A final test on the finished assembly is all that’s needed before the processor can be shipped to a manufacturer and ultimately used to power a computer.